1. Field of the Invention
The present invention generally relates to a static random access memory (SRAM), and more particularly, to a write operation of an SRAM.
2. Description of Related Art
Since the CMOS process reaches 65 nanometer level, the stability of an SRAM becomes challenged. Since the minimal dimension of a transistor is difficult to be controlled precisely and stochastic doping fluctuation has more significant influence with the process accuracy, the threshold of a transistor is easily varied, which causes a great negative impact on the write margin of the memory cells of an SRAM.
FIG. 1 is a circuit diagram of a memory cell of an SRAM, where the memory cell is a latch comprising two inverters, and the two inverters must be inverted during a write operation. In particular, during a write operation of the memory cell, the transistors PU and TG and the bit line BL together form a voltage-dividing circuit which has an equivalent circuit shown by FIG. 2. Referring to FIGS. 1 and 2, if the width and length of the above-mentioned transistors are varied or a stochastic doping fluctuation occurs so that the threshold of the transistor PU is reduced and/or the threshold of the transistor TG is increased, the voltage of the node nv1 is increased, which has a negative impact on inverting the inverters and reduces the write margin.
Referring to FIGS. 3 and 4, FIG. 3 is a signal timing diagram of the voltages of the word line WL and two nodes nv0 and nv1 of the memory cell in FIG. 1 as a write operation succeeds, wherein the voltages of the nodes nv0 and nv1 clearly indicate the two inverters are inverted during the effective duration of the word line voltage thereof and the write operation of data succeeds. FIG. 4 is a signal timing diagram showing the memory cell in FIG. 1 has a failed write operation, where due to the decreased write margin, the inverters are unable to be inverted during the effective duration of the word line voltage thereof so as to result in a failed write operation of data. Once a write operation fails, the SRAM exhibits unreliable performance, which is not allowable for computer applications.
There are several schemes today to increase the write margin of a memory cell. The above-mentioned schemes have a common feature of reducing the memory cell voltage during a write operation to increase the write margin. Referring to the voltage-dividing circuit of FIG. 2, reducing the cell voltage VDD below the turn-on voltage of the word line WL during a write operation can increase the equivalent resistance of the transistor PU when PU is turned on and thereby reduce the voltage of the node nv1, which facilitate to invert the two inverters. The conventional schemes for increasing the write margin are depicted as follows.
FIG. 5 is the circuit diagram provided by K. Zhang in his US Patent Application Publication No. 2006/0067134. The circuit is based on an idea of dual power supplies, where the high power voltage VDD_HI of a power supply circuit 501 is selected as the memory cell voltage during a read operation, and the low power voltage VDD_LOW of the power supply circuit 502 is selected as the memory cell voltage during a write operation. The circuit is disadvantageous in complexity of the circuit design and the timing control, because the scheme requires switching the circuit between the high power voltage VDD_HI and the low power voltage VDD_LOW corresponding to the read and write operations. Therefore, it is difficult to control the voltage stably. In addition, VDD_HI and VDD_LOW are fixed voltages and not varied with the fluctuation of the operation voltage VDD, so that the circuit is not suitable for an operation voltage VDD with larger fluctuation range.
FIG. 6 is a circuit diagram provided by RENESAS Technology Corp. in US Patent Application Publication No. 2006/0262628. The circuit is based on an idea of floating column voltage. During a write operation, the complementary voltage levels of the bit lines BL and BLB would turn off the p-channel metal oxide semiconductor field effect transistor (P-MOSFET) 603 for controlling the cell voltage VDD through an NAND gate 602 so as to float the cell power line 601. Moreover during the write operation, the n-channel metal oxide semiconductor field effect transistor (N-MOSFET) 604 is turned on, so that the charges on the cell power line 601 flow into the bit line BL along the dotted line direction shown in FIG. 6. The circuit is not suitable for a too long memory cell column (i.e., a memory column with many memory cell) because the length of the bit line affects its capacitance (e.g., capacitance of the cell power line 601). Excessive capacitance caused by the too long bit line lessens the reduction of the cell voltage and restricts the improvement of the write margin.
FIG. 7 is a circuit diagram provided by RENESAS Technology Corp. in the paper “A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability with Read and Write Operation Stabilizing Circuits”. The circuit is based on an idea of charge sharing for reducing the cell voltage, wherein in addition to the cell power line 701 which a memory cell column usually contains, the circuit further employs an additional metal line 702. During a write operation, the P-MOSFET 703 for controlling the cell voltage VDD is turned off and the N-MOSFET 704 is turned on, so that the charges on the cell power line 701 flow into the additional metal line 702 along the dotted line direction shown in FIG. 7 to reduce the cell voltage. The circuit has a disadvantage that the reduction of the cell voltage is hard to be precisely controlled because the reduction of the cell voltage depends on a ratio of the capacitances of the cell power line 701 vs. that of the additional metal line 702. The capacitances of the conductive lines are difficult to be precisely matched with each other, which affects the accuracy of the reduction of the cell voltage.